Many problems in microprocessor design arise with the increasing operational speed of the microprocessor. For example, the toggling action of a selection signal may adversely affect the accuracy of the output signal in response thereto. It is a big issue to be solved.
Please refer to FIG. 1A, in which a conventional 4*1 multiplexer M for outputting an output signal O from four signals P1˜P4 in response to a selection signal E is illustrated. The operation of the multiplexer M is referred to FIG. 1B. The multiplexer M comprises a decoder M0, a first, a second, a third and a fourth AND gates M1˜M4 and an OR gate M5. When the four signals P1˜P4 are inputted to the decoder M0, four decoding signals E1˜E4 corresponding thereto are generated in response to the selection signal E. The input signals P1˜P4 and the decoding signals E1˜E4 are operated by the AND gates M1˜M4, respectively, to output only one of the four input signals P1˜P4 at the same time. In order to achieve this purpose, only should one of the decoding signals E1˜E4 be at an enabling state, e.g. a high-level state, at the same time, and the others should be at a disabled state, e.g. a low-level state, so as to output the one of the four signals P1˜P4 corresponding to the high-level decoding signal. By changing the bit combination of the selection signal E, the bit states of the decoding signals E1˜E4 are changed so as to output another one of the signals P1˜P4.
Sometimes, two different ones of the four signals P1˜P4 are to be outputted continuously. The selection signal E will thus involve in toggling action. The waveform of the output signal O of the multiplexer M may be influenced by the toggling action. Please refer to FIG. 2, which exemplifies the problem resulting from the toggling action. In this example, the four input signals P1˜P4 are source signals derived from a high-frequency signal and generated by a phase-locked loop (PLL) circuit. There is a constant phase difference between every two adjacent ones of the source signals P1˜P4. For example, the phase difference is one clock unit. Further, it is desired that the first source signal P1 is to be outputted within the period from the time point t1 to the time point t6, and the third source signal P3 is to be outputted within the period t6˜t11. In other words, the selection signal E toggles at the time point t6. It is understood that the output signal O is supposed to be maintained at a high level from t1 to t11 because the first and the third source signals are continuously outputted without interruption. In practice, however, the state transition may lag to some extent. As shown in FIG. 2, it is common that while the first decoding signal E1 changes from the high-level state to the low-level state at the time point t6, the third decoding signal E3 does not change from the low-level state to the high-level state until the time point t7. Accordingly, the level of the output signal O within the period t6˜t7 will be unexpectedly low. Under this circumstance, the downstream device or circuit working in response to the output signal O is subject to error function.